Anti-electrostatic impact design of an integrated circuit chip is an essential guarantee on reliable working of the chip, and an effective ESD protection scheme requires a discharge device to rapidly enter a high-current discharge state when an ESD event is approaching, while keeping a turn-off state when the chip works normally. In an ESD protection design for the chip, a normal working voltage and an ESD event are generally differentiated through the amplitude and the rise time of a signal, and the ESD event has the characteristics of a very short rise time (in the order of a few hundred picoseconds to a few tens of nanoseconds) and a very high transient pulse amplitude. Whereas the power-up time of the normal working voltage is usually 4 to 5 orders longer than that of the ESD event, and the amplitude voltage of the normal working voltage is far lower than that of the ESD event.
The ESD protection design for the chip naturally involves the problem of a trigger mechanism for the discharge device. In a traditional device-level ESD protection design, a gate-grounded NMOS (N-mental-oxide-semiconductor) transistor is usually used as the discharge device, and when a pulse voltage applied to the drain terminal of the device is up to a certain extent, a parasitic BJT (bipolar junction transistor) device in the body of the NMOS transistor is turned on and enters a charge-discharge state. The trigger mechanism of this design scheme is a pure DC (direct current) trigger mechanism utilizing a parasitic current path in the body of the device, and whether the discharge device is turned on or not is completely determined by the amplitude of the voltage applied to the drain terminal regardless of the own rise time of the pulse. This trigger mechanism has the following characteristics: the design is simple and additional trigger circuit is not required, however, the turn-on of the discharge device is not quick enough and the discharge capacity is not high enough.
In order to solve the problems existed in the trigger mechanism above that the turn-on of the discharge device is not quick enough and the discharge capacity is not high enough, a designer usually uses an auxiliary circuit for carrying out transient identification on the ESD event, and whether an impact is the ESD event is judged by an RC detection circuit according to the rise time of a pulse, and if so, the gate electrode of the discharge device is pulled up so that a channel current participates in discharge of static charges. This trigger mechanism is pure transient trigger, and a typical circuit structure is shown in FIG. 1. A protection structure with the pure transient trigger mechanism has the advantage in that the turn-on time of the discharge device is very short when the ESD event is approaching, the discharge current is composed of both a current in the body of the discharge device and the channel current, thus a higher protection reliability is achieved relative to a gate-grounded protection scheme. However, the pure transient-triggered power-rail ESD clamp circuit is very sensitive to quick power-up and a high-frequency noise, and is prone to erroneous triggering phenomenon when the chip works normally. Meanwhile, as shown in FIG. 1, in order to enable discharge transistor to keep a turn-on state during the whole ESD event period, the designer will usually add an additional NMOS transistor Mfb to form a positive feedback, and the pure transient-triggered protection circuit with the feedback mechanism further faces to a serious latching-up problem after erroneous triggering.
Another trigger mechanism for the discharge device is a circuit-assisted pure DC trigger mechanism, as shown in FIG. 2, the main idea of this pure DC trigger mechanism design lies in that: when the chip works normally, a relatively low voltage amplitude is applied to VDD, a diode-connected NMOS transistor Mnc clamps a voltage at its own drain terminal to a logic high level, and at this moment, the discharge device Mbig keeps a turn-off state. When the ESD event is approaching, the voltage applied to the VDD instantly achieves a very high amplitude, so that the voltage at the drain terminal of the Mnc becomes a logic low state, and the discharge device is turned on through driving of a phase inverter so as to enter an ESD discharge mode. The circuit-assisted pure DC trigger mechanism has the following characteristics: firstly, a channel current and a volume current participate in charge discharge simultaneously, thus relatively high protection reliability is achieved. Secondly, the circuit-assisted pure DC trigger mechanism is insensitive to quick power-up and a high-frequency noise, and the problem of erroneous triggering during normal working can be substantially avoided as long as it is properly designed. However, the turn-on of the discharge device in the pure DC trigger mechanism is late, and the discharge device is turned on only after the voltage applied to VDD exceeds the trigger voltage thereof, while during the period from the ESD event rising to the trigger voltage of the discharge device from zero volt, the chip is still exposed to the ESD event, thus the reliability of the design scheme of the pure DC trigger mechanism is greatly reduced.